1. Field of the Invention
The invention relates to a full-wave rectifying device having an amplitude modulation function, and, in particular, to an integrated circuit (IC) device containing a full-wave rectifier having an amplitude modulation function which receives energy emitted from a transceiver via an external antenna and rectifies the energy into a DC power source for use by the IC device. The full-wave rectifier also receives a modulation code set by the IC device and then transmits it to the transceiver.
2. Description of Related Art
A typical IC is provided with an external power source. Batteries are generally used to provide a direct DC power source. Alternatively, an AC power source can be supplied which is then rectified into a DC power source. A common simple rectifying device is a full bridge rectifier. As shown in FIG. 1, conventional rectifier 1 consists of 4 diodes D1, D2, D3 and D4, and capacitor C.sub.s. A voltage at voltage point V.sub.cc represents a rectified voltage coupled to ground reference point GND through capacitor C.sub.s. An AC voltage between terminals V.sub.s1 and V.sub.s2 is rectified into a DC voltage by rectifier 1. The DC voltage is then stored in capacitor C.sub.s for application across load R.sub.L. When the AC voltage is in its positive half-wave period (V.sub.s1 &gt;V.sub.s2), diodes D1 and D3 are turned-on, while diodes D2 and D4 are turned-off. At this time, capacitor C.sub.s is charged by a current flowing through diode D1, capacitor C.sub.s and diode D3. When the AC voltage is in its negative half-wave period (V.sub.s1 &lt;V.sub.s2), diodes D2 and D4 are turned-on, while diodes D1 and D3 are turned-off. During this time, capacitor C.sub.s is charged by a current flowing through diode D2, capacitor C.sub.s and diode D4. The two charge states mentioned above alternate, thereby creating a power source at voltage point V.sub.cc for use by load R.sub.L. However, since parasitic devices formed on the junctions among these devices (depicted by parasitic transistors Q1 and Q2), which disable the rectifying circuit, are not eliminated, this type of rectifying circuit is not suitable for ICs, and particularly for CMOS ICs. The influence of these parasitic devices on the rectifying circuit will be described in more detail below.
When rectifying circuit 1 in FIG. 1 is made into an IC, that is, two PN junctions making up diodes D1 and D4 respectively, parasitic NPN transistor Q1 is formed by an N-type region of diode D1, a P-type region of diode D4, and an N-type region of diode D4. Similarly, another NPN parasitic transistor Q2 is also formed by an N-type region of diode D2, a P-type region of diode D3, and an N-type region of diode D3. When the AC voltage is in its positive half-wave period (V.sub.s1 &gt;V.sub.s2) base B and emitter E of parasitic transistor Q2 are forward biased to turn on parasitic transistor Q2, and thereby a great amount of charge current is created to directly flow through parasitic transistor Q2 instead of through capacitor C.sub.s. Therefore, the rectification efficiency is decreased, even to the point where there is no rectification at all. Similarly, the same problem caused by parasitic transistor Q1 occurs during the negative half-wave period.
Referring to FIG. 2, diodes D3 and D4 of FIG. 1 are replaced with NMOS devices N3 and N4 respectively which are manufactured by a P-well process, wherein the bulk and source of NMOS devices N3 (N4) are connected to each other and the drain and gate thereof are connected to each other. Parasitic NPN transistor Q3 (Q4) is formed by an N-type region (that is, an N-substrate connected to DC voltage point V.sub.cc of diode D1 (D2), the P-well region in which NMOS device N4 (N3) is located, and the N.sup.+ drain of NMOS device N4 (N3). When the AC voltage is in its positive half-wave period (Vs1&gt;Vs2), base B and emitter E of parasitic NPN transistor Q3 are forward biased to turn on parasitic NPN transistor Q3, thereby allowing a large amount of charging current to directly flow through parasitic NPN transistor Q3, and not through capacitor C.sub.s, resulting in decreased rectification efficiency or no rectification at all. Similarly, the same problem caused by parasitic NPN transistor Q4 occurs during the negative half-wave period.
Referring to FIG. 3, diodes D3 and D4 of FIG. 1 are replaced with PMOS devices P3 and P4 respectively, wherein the bulk (that is, N-substrate) of each PMOS device is connected to voltage point V.sub.cc, and the drain and gate of each PMOS device are connected to each other. Parasitic PNP transistor Q5 (Q6) is formed by the P.sup.+ source, bulk and P.sup.+ drain of parasitic PNP transistor P4 (P3). This parasitic transistor does not affect the operation of the rectifying circuit. However, since a voltage difference exists between the bulk and source of the PMOS transistor, a body effect occurs in PMOS P3 (P4) resulting in poor rectification efficiency and speed.
As can be seen from the above, using PMOS devices having poor rectification efficiency in place of the diodes is a better choice.
Referring to FIG. 4A, a conventional full-wave rectifying device having an amplitude modulation function is shown. External antenna ANT is made up of an inductor L and a capacitor C, one end of external antenna ANT being connected to terminal Vs1 and the other end being connected to terminal Vs2. The rectifying circuits shown in FIG. 4A and FIG. 3 are both manufactured by a P-well process. The main difference between them is that PMOS transistor P4 of FIG. 3 is replaced with NMOS transistor M.sub.N, wherein the bulk and source of NMOS transistor M.sub.N are connected to each other, and the gate of NMOS transistor M.sub.N receives signal modulation control signal S.sub.MOD transmitted from an IC. NMOS transistor M.sub.N chiefly functions as a modulating transistor. The modulation function can be implemented by controlling the on/off states of NMOS transistor M.sub.N to change the energy of the antenna inductor. However, parasitic NPN transistor Q.sub.N is formed by an N-type region (that is N-substrate) of diode D1, the P-well region of NMOS transistor M.sub.N and the N.sup.+ drain of NMOS transistor M.sub.N.
As for the operation of rectification, when an AC voltage is in its positive half-wave period (Vs1&gt;Vs2), diode D1 is turned on and capacitor C.sub.s is charged. At this point, a charge current flows to terminal V.sub.s2 via PMOS transistor P3, thereby accomplishing positive half-wave rectification. When the AC voltage is in its negative half-wave period (V.sub.s1 &lt;V.sub.s2), diode D2 is turned on, and capacitor C.sub.s is charged. At this point, the junction between base B and emitter E of parasitic transistor Q.sub.N is turned on, thereby accomplishing negative half-wave rectification. However, during the negative half-wave period, since terminal V.sub.s2 is positive with respect to terminal V.sub.s1, the junction between emitter E and base B of parasitic PNP transistor Q6 is forward biased, thereby turning on NPN transistor Q.sub.N resulting in a discharge of capacitor C.sub.s and affecting the rectification effect in the negative half-wave period.
Referring to FIG. 4B, an equivalent circuit of a full-wave rectifying device having an amplitude modulation function of FIG. 4A is depicted. An equivalent current source I.sub.M represents the external antenna, and R.sub.in (viewed from the both ends of the antenna towards the inside) represents an equivalent input resistor. The value of R.sub.in can be varied by controlling the degrees of the on-state of the M.sub.N transistor resulting in the voltage variation on the both ends of the antenna, thereby implementing the purpose of the amplitude modulation. Nevertheless, since the bulk of PMOS transistor P3 is connected to high-voltage V.sub.cc, the characteristics of PMOS transistor P3 are influenced by the body effect to cause its turned-on resistance to increase, such that the rectification efficiency is decreased. This affects the modulation index, which reduces the modulation efficiency.
Therefore, the disadvantages of the prior art are as follows:
(1) due to the influence caused by the PMOS body effect during the positive half-wave period, and the discharge of the capacitor C.sub.s resulting from the turned-on period of the transistor Q.sub.N during the negative half-wave period, the rectification efficiency is greatly reduced, resulting in an inability to endure a higher load.
(2) since the lower rectification efficiency during the negative half-wave period causes a lower voltage at voltage point V.sub.cc, the voltage level for controlling the turned-on period of NMOS transistor M.sub.N is relatively decreased. Therefore, the degree of the turned-on period of NMOS transistor M.sub.N is not complete, and the lower amplitude of wave trough can not be acquired. In addition, due to the body effect of the PMOS, the modulation efficiency becomes poor during transmission.
(3) since NPN transistor Q.sub.N and PNP transistor Q6 exist simultaneously, if parameters such as current amplification ratio .beta. of the parasitic transistor in the process can not be controlled well, an SCR formed by the transistors Q.sub.N and Q6 easily produces latch-up.